Custom «The Inverter Circuits» Essay Paper Sample
Table of Contents
- A report to compare two inverter circuits
- Cascaded multilevel inverters
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- The required capacitance of DC capacitors
- For the conventional multipulse inverters
- For the cascade inverters
- Comparison of needed capacitance
- Simulation and experimental results
- On line joint phase RSS
- The look up table joint phase RSS
- Computer simulation results
- Steady state study
- Dynamic studies
- Laboratory validation
- Related Comparison essays
A report to compare two inverter circuits
Cascaded multilevel inverters
The idea of multilevel inverters was brought into being 20 years ago. The purpose of its introduction was to perform the role of converting power in multiple voltage steps to acquire improved quality of power, to reduce switching losses, better compatibility of electromagnetic and higher capabilities on voltage.
The 3/3 cascaded inverter is as shown below. A connection of a three level inverter on either sides of the motor winding gives it topology. For practical purposes, the inverters may consist of several levels of voltage. In this paper we will establish a control to regulate to regulate the dc voltage so that a single dc source voltage is needed. This gives unique merits for Naval propulsion which functions from a single source. However, the conditioning inverter is fed by a capacitor bank; the loaded inverter must be rated for the all the amount of the loaded power. Based on these conditions, the inverter responsible for conditioning now becomes an additional expense justifiable by the quality of high power. A substitute means to reduce harmonics is to include passive filter components to the loaded inverter which also adds on the cost. As such the passive components will alter their effect on the system harmonics as the operating point of the drive is varied. Elimination of voltage source for the inverter responsible for conditioning is that it is no longer present for driving the motor under such circumstances where faults exist in the loaded inverter. The most notable feature relating to operation of faults in ship propulsion loads is that low amounts of power is required to operate in a survivable situation. This is because the load power fluctuates as the speed cubed, of only 12% of maximum power is needed to function at a rated speed of half.
The required capacitance of DC capacitors
As described earlier the cascade inverter has the simplest structure and the fewer components when related with the conventional multipulse inverter, the flying capacitor multilevel inverter, and the diode clamped multilevel inverter. However the recent inverter's necessities are higher than the diode clamped multilevel inverter and the conventional multipulse inverter. Therefore the needed capacitance of the cascade inverter will be devised and related with that of conventional multipulse inverter.
For the conventional multipulse inverters
It is normally required that an SVG has the capacity to produce 100% negative succession var for unbalanced loads in the event of phase fault. Hence the needed capacitance of dc capacitors used in the conventional inverter should facilitate this production of 100% negative succession.
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For the cascade inverters
For the suggested cascade inverter calculation of needed capacitance of each unit of FBI dc capacitors is direct and routinely accommodates both positive and negative sequence reactive power.
Comparison of needed capacitance
This will involve comparison of two systems. An experimental prototype has been devised to illustrate the suitability of the new inverter under test.
Simulation and experimental results
To illustrate the suitability of the new inverter a SVG prototype applying an 11- level wye connected cascade inverter was developed.
In general the new multilevel voltage source cascade inverter has been suggested. It has many features such as easy modularity, packaging and least component count. This acts as a solution to most major problems of the flying capacitor multilevel inverter, conventional multipulse inverter, and diode clamped multilevel inverter.
This inverter can applied in static var generation, series compensation, power line conditioning, and voltage balancing. This is due to individual dc capacitor voltage can be self sustained and can be controlled independently without extra dc sources. This has been practically validated through simulated and illustrated outcomes. It has been also established that the needed capacitance of dc capacitors is nearly similar as that of the conventional inverter for practical SVG applications.
Its topology can be easily adapted to other applications like fuel cell and photovoltaic utility interface systems where they are supplied by isolated dc sources.
Cascade-3/3 multilevel inverter
In reference to figure 1, assume that the capacitors are charged half way of their relevant dc bus voltage, line to ground voltages of the upper and lower voltages may be expressed using the following relationship.
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The level eleven flying capacitor multilevel inverter is well replicated through the use of MATLAB; the inverter supplies a well balanced three phase voltage to an induction motor. This has an output balance three phase voltage of 400V, 50HZ.
The charging and discharging of flying capacitor facilitates an individual voltage across each flying capacitor of Vdc/3. The fluctuation of voltage in flying capacitor is small. This can be lowered by raising capacitance value and carrier frequency.
The flying capacitor multilevel inverter voltage source modulation can be achieved in a multilevel inverter system by applying the sine triangle method. The way to go about this is by defining duty cycles for each phase. The three duty cycles are related to a set of triangular waveforms to generated switching states for the individual phase.
To be in apposition to achieve a desirable multilevel output voltage outcome, the voltage available on all the six capacitors, that is, two per phase must be retained at a constant level. Nonetheless, the currents have varied effects on the charging and the discharging of the capacitor. This will try to destabilize the capacitor voltages. Under this circumstance the redundant switching states turn into the core component for balancing voltages in the capacitor.
Due to the availability of various conduction paths under each phase which can give the similar voltage levels whereas possessing the various characteristics of a charging capacitor, per phase redundancy can be applied as you select a path with a good balancing in performance. With the increase in the number of attained voltage levels, the number of present per phase redundant states reduces. In this instance the switching states of the three phases can be used to balance the voltages of a capacitor when incremented or decremented this is because the result is zero sequence line to ground voltage. However this does not interfere with the load phase voltage. The line to ground voltages of all the phases may simultaneously be changed using the idea of joint phase redundant state selection method. Even so all this takes place without interference on the load voltages. This is as a result of universal phases which cancel out when looking line to line voltages or line to neutral voltages. Despite the fact that the load voltages are not subject to change, the choosing of the right joint state can improve the balancing situation of the capacitor. In this paper we will discuss the two joint phase redundant state selection algorithms.
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On line joint phase RSS
In the case where phase current measurements are present direct balancing algorithm. With the appropriate levels for the individual joint redundant states are regarded. The algorithm lowers the error between the ideal capacitor values and capacitor voltages. This therefore offers the best choice to raise the performance of the general balancing of voltages of the six capacitors.
The look up table joint phase RSS
In this method the direction of the load currents of the three phase must be known. It s from here that the direction of the capacitor currents are established basing on the transistor switching states. This is from 2 to 3. The desired levels for individual phase are determined by the multilevel modulator subsequently consideration of all joint redundant states and per phase sub choices follows. The capacitor balancing situation is determined by capacitor current direction flags. If the capacitor is overcharged and its direction is positive, this redundant state will therefore regulate the capacitor voltage. It also follows that if the capacitor is undercharged and the current direction is negative, the redundant state will also aid in regulating the capacitor voltage. The charging and discharging characteristics of individual state are described by balancing performance index when selected. The highest performance indexes of the switching states are selected. The switching states' performance indexes in all the possible the possible circumstances are calculated prior and related so that a better state can be achieved directly from a table basing on the capacitor voltage flags and direction flags of load currents. The flags therefore make up the indexes table.
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Computer simulation results
Steady state study
The computer simulation method was established to ascertain the method that has been suggested. The JRSS effect is observed where the bus clamps to the highest and lowest levels. Nonetheless, due to the fact that all this is performed in all the phases the line to line voltage and line to neutral voltages are not interfered.
In this method an induction motor with vector control and an outer speed loop is driven by a three cell flying capacitor multilevel inverter. Whereby, the speed command is ramped up to 188 Radians per second. In the load, the step change of 0 to 20 Nm is supplied at 4.5s then the command speed is lowered to zero with the load on the motor. In this instance the input source is set to dc voltage of 660v. The capacitor voltages, torque and speed therefore portray a good balance in the entire dynamic studies as the power factor and the modulation indexes change over a wide variety.
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To be in a position to declare the concept for use, a three cell 5 level flying capacitor multilevel inverter was built in the laboratory. The DSP method of programming is used to program the modulation to give the outputs of the desired switching states. The conversion from analog to digital is performed on the capacitor voltages and the phase current in order to establish capacitor voltage flag and the current direction. The above information therefore alongside the desired switching state gives rise to the address of the desired state in the redundant selection state table. All the redundant states are computed offline before being programmed into a complex programmable logic device.
In general the redundant switching states, important to capacitor voltage balancing, are sacrificed to attain a higher number of output voltage levels. The two joint phase redundant state selection algorithms were suggested to maintain the capacitor voltages constant. The simulation result illustrates the effectiveness of the individual algorithm. One of the algorithms was confirmed through an experiment in laboratory on a motor drive system. In that experiment, the three cell flying capacitor inverter which specifically runs in the four level mode was lengthened to accommodate a five level operation. It was also proved via simulation that the three cell inverter can attain eight level operation for applications entailing reactive power compensation.
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The following are the characteristics that put flying capacitor a head of the rest inverters and make them a favorable option for use:
It is capable of handling high voltages and applications of high power as compared to the rest of the inverters.
It is capable to switch each device at a single instance per line circle and give rise to a multistep staircase voltage waveform moving close to a pure sinusoidal output voltage by raising the level number.
The availability of the cascaded connection makes it possible for the connection of lots of single phase, full bridge inverter units where each bridge is supplied by separate Dc power source. It does not therefore require voltage sharing circuits or matching of the voltages of the devices responsible for switching.
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It has got an easier layout or package due to its simplicity of structure and low component count.